1) Field of the Invention
This invention relates generally to the structure and fabrication of a semiconductor device and more particularly to the fabrication of a carbon containing layer near doped regions in a transistor.
2) Description of the Prior Art
Semiconductor devices such as field effect transistors (FETs) have a source region, and a drain region formed in a semiconductor substrate and a gate formed over the channel region. The source and drain are formed in a semiconductor substrate by introducing impurities (dopants) into the substrate. The semiconductor body separates the source region and the drain region. The dopants used to form the source and drain regions are of a different polarity (n-type or p-type) than the semiconductor substrate body surrounding the source and drain regions. Consequently, substantially no current will pass from the source to the semiconductor body or from the drain to the semiconductor body.
There is a space-charge layer (or channel) which separates both the source region from the semiconductor body and the drain region from the semiconductor body.
The usual method of introducing dopant atoms is ion implantation. During ion implantation, dopant atoms are ionized, accelerated and directed at a silicon substrate. They enter the crystal lattice of the silicon substrate, collide with silicon atoms and gradually lose energy, finally coming to rest at some depth within the lattice. The average depth can be controlled by adjusting the acceleration energy. The dopant dose can be controlled by monitoring the ion current during implantation. The principal side effect—disruption of the silicon lattice caused by ion collisions—is removed by subsequent heat treatment, i.e., annealing. Annealing is required to repair lattice damage and place dopant atoms on substitutional sites within the silicon substrate where they will be electrically active. Rapid thermal annealing is a term that covers various methods of heating wafers for short periods of time, e.g., 100 seconds, which enable almost complete electrical activation with diffusion of dopant atoms occurring within what had been previously regarded as tolerable limits.
However, during the anneal, damage from the ion implantation process, in the form of point defects, migrates laterally from the source and/or drain and into the semiconductor body and enhances dopant diffusion. This enhanced diffusion, known as transient enhanced diffusion (TED) changes the carefully tailored profile in the body of the device.
Transient enhanced diffusion occurs during post-implant annealing and arises from the fact that the diffusion of dopant atoms, particularly boron (B) and phosphorus (P), is undesirably enhanced by excess silicon (Si) self-interstitials generated by the implant. The generation of excess Si self-interstitials by the implant also leads to a phenomenon herein referred to as dynamic clustering whereby implanted dopant atoms form clusters or agglomerates in a semiconductor layer. These clusters or agglomerates are immobile and electrically inactive.
Recent investigations have been aimed at untangling the mechanisms of dopant diffusion in order to provide a sound basis for simulation programs designed to predict dopant diffusion during device processing. An additional challenge is the development of processing-compatible methods of controlling the diffusion of dopant atoms.
The FIG. 10 shows a typical implant doping profile at different implantation energies. Rp which is the projected range of the implantation is measured from the surface of the substrate in to the maximum region where the dopant lies.
The more relevant technical developments in the patent literature can be gleaned by considering the following:
U.S. Pat. No. 6,153,920 Gossmann, et al. Nov. 28, 2000—Process for controlling dopant diffusion in a semiconductor layer and semiconductor device formed thereby.
U.S. Pat. No. 5,731,626 Eaglesham, et al and U.S. Pat. No. 6,043,139 Eaglesham, et al.—Process for controlling dopant diffusion in a semiconductor layer—Diffusion of ion-implanted dopant is controlled by incorporating electrically inactive impurity in a semiconductor layer by at least one crystal growth technique.
U.S. Pat. No. 6,576,535 Drobny, et al. Jun. 10, 2003—doped epitaxial layer.
Chung Foong Tan, Eng Fong Chor, Jinping Liu, Hyeokjae Lee, Elgin Quek, and Lap Chan, “Influence of substitutional carbon incorporation on implanted-indium-related defects and transient enhanced diffusion”, Applied Physics Letters Vol. 83(20) pp. 4169–4171. Nov. 17, 2003.
Nishikawa, S., et al., “Reduction of transient boron diffusion in preamorphized Si by carbon implantation,” Appl. Phys. Lett., 60(18), May 4, 1992.
King et al., “Defect evolution of low energy, amorphizing germanium implanted in silicon”, Journal of Applied Physics, Vol. 93, # 5, March 2003, pp. 2449–2452.
Nishikawa et al., “Elimination of secondary defects in preamorphized Si by C+ implantation”, Appl. Phys. Lett 62 (3) 18 Jan. 1993, pp. 303–305.
Noda, Indium segregation into dislocation loops induced by ion implanted damage in Si”, Journal Of Applied Physics v. 93, # 3, 1 Feb. 2003, pp. 1428–1431.